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39
An InterconnectCentric Design Flow for Nanometer Technologies
 Proceedings of the IEEE
, 1999
"... As the IC devices is scaled into nanometer dimen sions and operates in gigahertz frequencies, interconnect design and optimization have become critical in determining the system performance and reliability. ..."
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Cited by 80 (26 self)
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As the IC devices is scaled into nanometer dimen sions and operates in gigahertz frequencies, interconnect design and optimization have become critical in determining the system performance and reliability.
An Enhanced Multilevel Routing System.
, 2002
"... In this paper, we present several novel techniques that make the recently published multilevel routing scheme [19] more effective and complete. Our contributions include: (1) resource reservation for local nets during the coarsening process, (2) congestiondriven, graphbased Steiner tree constructi ..."
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Cited by 30 (3 self)
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In this paper, we present several novel techniques that make the recently published multilevel routing scheme [19] more effective and complete. Our contributions include: (1) resource reservation for local nets during the coarsening process, (2) congestiondriven, graphbased Steiner tree construction during the initial routing and the refinement process and (3) multiiteration refmement considering the congestion history. The experiments show that each of these techniques helps to improve the completion rate considerately. Compared to [19], the new routing system reduces the number of failed nets by 2x to 18x, with less than 50% increase in runtime in most cases.
A reconfigurable architecture for hybrid CMOS/nanodevice circuits
 Hangzhou University
"... This report describes a preliminary evaluation of performance of a cellFPGAlike architecture for future hybrid “CMOL ” circuits. Such circuits will combine a semiconductortransistor (CMOS) stack and a twolevel nanowire crossbar with molecularscale twoterminal nanodevices (programmable diod ..."
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Cited by 29 (5 self)
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This report describes a preliminary evaluation of performance of a cellFPGAlike architecture for future hybrid “CMOL ” circuits. Such circuits will combine a semiconductortransistor (CMOS) stack and a twolevel nanowire crossbar with molecularscale twoterminal nanodevices (programmable diodes) formed at each crosspoint. Our cellbased architecture is based on a uniform CMOL fabric of “tiles”. Each tile consists of 12 fourtransistor basic cells and one (four times larger) latch cell. Due to high density of nanodevices, which may be used for both logic and routing functions, CMOL FPGA may be reconfigured around defective nanodevices to provide high defect tolerance. Using a semicustom set of design automation tools we have evaluated CMOL FPGA performance for the Toronto 20 benchmark set, so far without optimization of several parameters including the power supply voltage and nanowire pitch. The results show that even without such optimization, CMOL FPGA circuits may provide a density advantage of more than two orders of magnitude over the traditional CMOS FPGA with the same CMOS design rules, at comparable time delay, acceptable power consumption and potentially high defect tolerance.
The Rectilinear Steiner Arborescence Problem is NPComplete
, 2000
"... Given a set P of points in the first quadrant, a Rectilinear Steiner Arborescence (RSA) is a directed tree rooted at the origin, containing all points in P , and composed solely of horizontal and vertical edges oriented from left to right, or from bottom to top. The complexity of finding an RSA with ..."
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Cited by 28 (0 self)
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Given a set P of points in the first quadrant, a Rectilinear Steiner Arborescence (RSA) is a directed tree rooted at the origin, containing all points in P , and composed solely of horizontal and vertical edges oriented from left to right, or from bottom to top. The complexity of finding an RSA with the minimum total edge length for general planar point sets has been a major open problem, and has important applications in VLSI. In this paper, we prove the problem is strongly NPcomplete. The proof also shows the Euclidean version of the Steiner Arborescence problem is NPhard.
Physical hierarchy generation with routing congestion control
 In Proc. Int. Symp. on Physical Design
, 2002
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Multilevel Global Placement with Congestion Control
 IEEE Trans. on ComputerAided Design of Integrated Circuits and Systems
, 2003
"... In this paper, we develop a multilevel global placement algorithm (MGP) integrated with fast incremental global routing for directly updating and optimizing congestion cost during physical hierarchy generation. Fast global routing is achieved using a fast twobend routing and incremental Atree algo ..."
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Cited by 21 (6 self)
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In this paper, we develop a multilevel global placement algorithm (MGP) integrated with fast incremental global routing for directly updating and optimizing congestion cost during physical hierarchy generation. Fast global routing is achieved using a fast twobend routing and incremental Atree algorithm. The routing congestion is modeled by the wire usage estimated by the fast global router. A hierarchical area density control is developed for placing objects with significant size variations. Experimental results show that, compared to GORDIANL, the wire lengthdriven MGP is 46.7 times faster and generates slightly better wire length for test circuits larger than 100 000 cells. Moreover, the congestiondriven MGP improves wiring overflow by 45%74% with 5% larger bounding box wire length but 3%7% shorter routing wire length measured by a graphbased Atree global router.
MR: A new framework for multilevel fullchip routing
 IEEE Trans. CAD
, 2004
"... Abstract—In this paper, we propose a novel framework for multilevel fullchip routing considering both routabilityand performance called MR. The twostage multilevel framework consists of coarsening, followed byuncoarsening. Unlike the previous multilevel routing, MR integrates global routing, detai ..."
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Cited by 20 (8 self)
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Abstract—In this paper, we propose a novel framework for multilevel fullchip routing considering both routabilityand performance called MR. The twostage multilevel framework consists of coarsening, followed byuncoarsening. Unlike the previous multilevel routing, MR integrates global routing, detailed routing, and resource estimation, together at each level of the framework, leading to more accurate routing resource estimation during coarsening and thus facilitating the solution refinement during uncoarsening. Further, the exact routing information obtained at each level makes MR more flexible in dealing with various routing objectives (such as crosstalk, power, etc.). Experimental results show that MR obtains significantlybetter routing solutions than previous works. For example, for a set of 11 commonlyused benchmark circuits, MR achieves 100 % routing completion for all circuits, while the previous multilevel routing, the threelevel routing, and the hierarchical routing can complete routing for only2, 0, 2 circuits, respectively. In particular, the number of routing layers used by MR is even smaller. We also have performed experiments on timingdriven routing. The results are also verypromising.
MARS–A Multilevel FullChip Gridless Routing System
 IEEE TCAD
, 2005
"... Abstract—This paper presents MARS, a novel multilevel fullchip gridless routing system. The multilevel framework with recursive coarsening and refinement allows for scaling of our gridless routing system to very large designs. The downward pass of recursive coarsening builds the representations of ..."
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Cited by 17 (1 self)
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Abstract—This paper presents MARS, a novel multilevel fullchip gridless routing system. The multilevel framework with recursive coarsening and refinement allows for scaling of our gridless routing system to very large designs. The downward pass of recursive coarsening builds the representations of routing regions at different levels while the upward pass of iterative refinement allows a gradually improved solution. We introduced a number of efficient techniques in the multilevel routing scheme, including resource reservation, graphbased Steiner tree heuristic and historybased iterative refinement. We compared our multilevel framework with a recently published threelevel routing flow [1]. Experimental results show that MARS helps to improve the completion rate by over 10%, and the runtime by II U. Index Terms—Design automation, routing optimization methods, very large scale integration (VLSI). I.
InterconnectDriven Floorplanning with Fast Global Wiring Planning and Optimization
 In Proc. SRC Tech. Conference
, 2000
"... This paper presents an interconnectdriven floorplanning (IDFP) flow and algorithm integrated with multilayer global wiring planning (GWP). It considers a number of interconnect performance optimizations during floorplanning, including interconnect topology optimization, layer assignment, buffer in ..."
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Cited by 12 (0 self)
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This paper presents an interconnectdriven floorplanning (IDFP) flow and algorithm integrated with multilayer global wiring planning (GWP). It considers a number of interconnect performance optimizations during floorplanning, including interconnect topology optimization, layer assignment, buffer insertion, wire sizing and spacing. It also includes fast routability estimation and performancedriven routing for congestion control. Our experiments on the SUN picoJavaII TM core test circuit show that over 74% delay reduction can be achieved using our interconnectdriven floorplanner, compared to a conventional floorplanner without consideration of interconnect performance optimization/planning. We expect that IDFP with GWP will play a central role in designing interconnectlimiting, highperformance integrated circuits. 1 Introduction Global interconnect is commonly recognized as a key factor for designing highperformance integrated circuits, as VLSI process technology migrates into...
A Catalog of Hanan Grid Problems
 Networks
, 2000
"... We present a general rectilinear Steiner tree problem in the plane and prove that it is solvable on the Hanan grid of the input points. This result is then used to show that several variants of the ordinary rectilinear Steiner tree problem are solvable on the Hanan grid, including  but not li ..."
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Cited by 10 (2 self)
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We present a general rectilinear Steiner tree problem in the plane and prove that it is solvable on the Hanan grid of the input points. This result is then used to show that several variants of the ordinary rectilinear Steiner tree problem are solvable on the Hanan grid, including  but not limited to  Steiner trees for rectilinear (or isothetic) polygons, obstacleavoiding Steiner trees, group Steiner trees and prizecollecting Steiner trees. Also, the weighted region Steiner tree problem is shown to be solvable on the Hanan grid; this problem has natural applications in VLSI design routing. Finally, we give similar results for other rectilinear problems. 1 Introduction Assume we are given a finite set of points S in the plane. The Hanan grid H(S) of S is obtained by constructing vertical and horizontal lines through each point in S. The main motivation for studying the Hanan grid stems from the fact that it is known to contain a rectilinear Steiner minimum tree (RSMT)...